(a) Field of the Invention
The present invention relates to a thin film transistor array panel for a liquid crystal display and a method for manufacturing the same, especially to a method for manufacturing a thin film transistor array panel with a reduced number of photolithography steps.
(b) Description of the Related Art
A liquid crystal display (LCD) is one of the most popular FPDs (flat panel displays). The LCD has two panels having electrodes for generating electric fields and a liquid crystal layer interposed therebetween. The transmittance of incident light is controlled by the intensity of the electric field applied to the liquid crystal layer.
In the most widely used LCD, the field-generating electrodes are provided at both panels, and one of the panels has switching elements such as thin film transistors (TFTs).
In general, a thin film transistor array panel is manufactured by photolithography using a plurality of photomasks, and five or six photolithography steps are used. The high cost for the photolithography process makes it desirable to reduce the number of the photolithography steps. Even though a few manufacturing methods using only four photolithography steps are suggested, these methods are not easy to accomplish.
Now, a conventional method of manufacturing a thin film transistor array panel using four lithography steps will be described.
First, a gate wire of aluminum or aluminum alloy are formed on a substrate by using a first mask. A gate insulating layer, an amorphous silicon layer, an n+ amorphous silicon layer and a metal layer are sequentially deposited. The metal layer, the n+ amorphous silicon and the amorphous silicon layer are patterned by using a second mask. At this time, gate pads of the gate wire is covered only with the gate insulating layer. An ITO (indium tin oxide) layer is deposited and patterned by using a third mask. At this time, the portions of the ITO layer over the gate pads are removed. After the metal layer and the n+ amorphous silicon layer thereunder are patterned by using the patterned ITO layer as an etch mask, a passivation layer is deposited. A complete thin film transistor array panel is obtained by patterning the passivation layer and gate insulating layer thereunder using a fourth mask, thereby removing the portion of the passivation layer and the gate insulating layer on the gate pads.
As a result, the gate pads of aluminum or aluminum alloy are exposed in the conventional manufacturing method of using four masks. The aluminum and the aluminum alloy cannot stand against physical and chemical variations and are vulnerable to damage and oxidation, despite their advantages of low resistivity. To compensate this matter, gate lines are formed to have multiple-layered structure or made of materials that can stand against the physical and chemical changes. However, the former makes the manufacturing process complicated, and the latter may result in a high resistivity problem.
It is therefore an object of the present invention to provide new methods for manufacturing a thin film transistor array panel for LCDs with a reduced number of photolithography steps.
It is another object of the present invention to protect gate pads of LCDs.
It is the other object of the present invention to prevent the LCD""s current leakage.
These and other objects are achieved, according to the present invention, by patterning the gate insulating layer, the semiconductor layer, the ohmic contact layer and the data conductor layer at a time.
According to the present invention, a gate wire is formed on an insulating substrate by a first photolithography process. A quadruple layers including a gate insulating layer, a semiconductor layer, an ohmic contact layer and a data conductor layer is deposited on the insulating substrate and the gate wire and formed by a second photolithography process. A conductive pattern is formed on the data conductor layer and the area surrounded by the data conductor layer by a third photolithography process. Then, the portion of the data conductor layer not covered by the conductive pattern is etched out to form a data wire and the ohmic contact layer not covered by the data wire is also etched out. Finally, a passivation layer pattern on the conductive pattern is formed by a fourth photolithography process.
At this time, the gate wire may include a plurality of gate lines extended to a first direction, gate electrodes that are branches of the gate line and gate pads connected to an end of the gate line and receiving a scanning signal from an external circuit. The quadruple layers may have first contact holes exposing the gate pad, and the passivation layer may have second contact holes exposing the first contact hole.
The gate wire may include a plurality of gate lines extended to a first direction, gate electrodes that are branches of the gate line and gate pads connected to an end of the gate line and receiving a scanning signal from an external circuit. The quadruple layers may have first contact holes exposing the gate pad. The conductive pattern may include first conductive patterns connected to the gate pad through the first contact hole, and the passivation layer may have second contact holes exposing the first conductive pattern.
The gate wire may include a plurality of gate lines extended to a first direction, gate electrodes that are branches of the gate line and gate pads connected to an end of the gate line and receiving a scanning signal from an external circuit. The data wire may include a plurality of data lines extended to a second direction and crossing the gate line, data pads connected to an end of the data line and receiving an image signal from an external circuit, source electrodes connected to the data line and adjacent with the gate electrode, and drain electrodes located at the opposite side of the source electrode with respect to the gate electrode. The conductive pattern may include a plurality of first conductive patterns formed on the data line, the source electrode and the data pad, second conductive patterns formed on the drain electrode, and pixel electrodes connected to the second conductive pattern and formed in the area surrounded by the gate line and the data line. The passivation layer may have first openings exposing the pixel electrode and second openings exposing the first conductive pattern on the data pad. The passivation layer may have third openings exposing a part of the semiconductor layer between the adjacent two data line. The step may further comprise a step of etching the exposed portion of the semiconductor layer to separate the semiconductor layer under the two data line from each other. The pixel electrode may be overlapped with the previous gate line and the portion of the semiconductor layer sandwiched between the pixel electrode and the gate line is isolated from the other portion.
The gate insulating layer may include a first portion formed between the gate pads and between the data pads, the passivation layer may have a fourth opening exposing the first portion of the gate insulating layer. The portion of the semiconductor layer located on the first portion of the gate insulating layer may be removed to separate the portions of the semiconductor layer under the gate pads and the data pads.
The passivation layer may cover the edge of the pixel electrode. The first opening exposes the edge of the pixel electrode. A storage wire overlapped with the pixel electrode may be formed on the substrate, the quadruple layers may be formed on the storage wire, and the portion of the semiconductor layer sandwiched between the storage wire and the pixel electrode is isolated from the other portion.
The passivation layer may have a trench exposing the portion of the semiconductor layer between the first conductive pattern and the pixel electrode and between the adjacent pixel electrodes, and further comprising a step of etching the exposed semiconductor layer through the trench. The gate line may include two main lines and branches connecting the two main lines, and the pixel electrode may be overlapped with a part of the gate line. The source electrode may have a concave part and the end part of the drain electrode may be located in the concave part.
The conductive pattern may be made of a transparent conductor such as indium-tin-oxide.
The forming step of the quadruple layers may comprise the substeps of coating a photoresist layer on the data conductor layer, patterning the photoresist layer to be a pattern of which thickness is varying depending on the location by exposure and development, etching the quadruple layers along with the photoresist layer pattern to expose the gate pad, to form a data wire leaving the source electrode and the drain electrode connected to each other, and to expose the portion of the gate insulating layer between the data wires. A first portion, the thinnest portion of the photoresist layer, may be formed on the gate pad. A second portion, the thickest portion, may be formed on the data wire where the source electrode and the drain electrode are connected to each other. A third portion that is thicker than the first portion and thinner than the second portion may be formed between the second portions. The exposure of the photoresist layer may be performed by using a photomask having at least three parts of which transmittance are different from each other. A portion of the gate insulating layer may be removed to expose ends of the gate wire by the second photolithography process. The conductive pattern may include first conductive patterns contacting with the exposed end of the gate wire. Contact holes exposing the first conductive pattern may be formed in the passivation layer by the fourth photolithography process.
According to the present invention, a thin film transistor array panel is provided. The thin film transistor array panel comprises a gate wire formed on an insulating substrate and including a plurality of gate lines extending to a first direction, gate electrodes connected to the gate line, and gate pads connected to an end of the gate line, a gate insulating layer having contact holes exposing the gate pad and formed in a matrix shape on the gate wire and the substrate, a semiconductor layer formed on the gate insulating layer, a data wire formed on the semiconductor layer and including a plurality of data lines extending to a second direction to cross the gate line, source electrodes adjacent to the gate electrode, drain electrode separated from the data line and the source electrode and located at the opposite side of the source electrode with respect to the gate electrode, and data pads connected to an end of the data line, a conductive pattern including a plurality of first patterns formed on the source electrode and the data line, second patterns formed on the drain electrode, third patterns formed on the data pad, and pixel electrodes connected to the second pattern, and a passivation layer formed on the conductive pattern, the semiconductor pattern and the substrate, and having a plurality of first openings exposing the pixel electrode, second openings exposing the gate insulating layer between the two adjacent data lines, third openings located on the gate pad, and fourth openings exposing the third pattern. At this time, the data wire is only formed between the conductive pattern and the semiconductor layer, the semiconductor layer is formed on the whole gate insulating layer except the portion under the second opening, and the portions of the semiconductor layer under the two adjacent data lines are separated from each other.
At this time, the thin film transistor array panel may further comprise a contact layer formed between the semiconductor layer and the data wire to have the same layout as the data wire and to reduce the contact resistance between the semiconductor layer and the data wire. The conductive pattern further includes a fourth pattern connected to the gate pad through the contact hole and the third opening exposes the fourth pattern. The pixel electrode may be overlapped with the adjacent gate line and the portion of the semiconductor layer sandwiched between the pixel electrode and the gate line is isolated from the other portion. The gate insulating layer may include a first portion formed between the two gate pads and the two data pads, the passivation layer has fifth openings exposing the first portion of the gate insulating layer, and the semiconductor layer is not formed under the fifth opening. The passivation layer may cover the edge of the pixel electrode. The first opening may expose the edge of the pixel electrode. The thin film transistor array panel may further include a storage wire formed on the substrate, overlapped with the pixel electrode and covered by the gate insulating layer, wherein the portion of the semiconductor layer sandwiched between the storage wire and the pixel electrode is isolated from the other portion. The conductive pattern may be made of indium-tin-oxide.
According to the present invention, a thin film transistor array panel may be manufactured by a method comprising the steps of forming a gate wire including a plurality of gate lines and gate pads by a first photolithography process. The next step is depositing a first insulating layer, a semiconductor layer, an ohmic contact layer and a metal layer on the gate wire and forming a metal layer pattern, an ohmic contact layer pattern, a semiconductor layer pattern and a first insulating layer pattern that have a matrix shape layout overlapping the gate wire except the gate pad by a second photolithography process. The next step is depositing a transparent conductor layer, forming a transparent conductor pattern including a pixel electrode, a plurality of redundant data lines, redundant source electrodes, redundant drain electrodes, redundant data pads and redundant gate pads by a third photolithography process. Following is etching out the portion of the metal layer not covered by the transparent conductor pattern and the ohmic contact layer thereunder, depositing a second insulating layer, forming a passivation layer pattern having openings respectively exposing the gate pad, the data pad, the pixel electrode and the portion of the semiconductor layer connecting the adjacent data line, and etching out the portion of the semiconductor layer exposed through the openings.
At this time, the manufacturing method may further comprise an etching step of the first insulating layer under the exposed portion of the semiconductor layer after the etching step of the exposed portion of the semiconductor layer.
According to the present invention, a thin film transistor array panel may also be manufactured by a method comprising the steps of forming a gate wire including a plurality of gate lines and gate pads by a first photolithography process. The next step is depositing a first insulating layer, a semiconductor layer, an ohmic contact layer and a metal layer on the gate wire and patterning the metal layer, the ohmic contact layer, the semiconductor layer and the first insulating layer to form a metal layer pattern, an ohmic contact layer pattern and a semiconductor layer pattern that are separated into two pieces at least on the gate wire and a first insulating layer pattern covering the gate wire except for the gate pad. The following step is depositing a transparent conductor layer and forming a transparent conductor layer pattern by a third photolithography process. The next step is etching the portion of the metal layer not covered by the transparent conductor layer pattern and the ohmic contact layer thereunder. The final step is to form a data wire including a plurality of data pads, source and drain electrodes and ohmic contact layer pattern thereunder, depositing a second insulating layer, and forming a passivation layer pattern at least having contact holes exposing the gate pad and the data pad by a fourth photolithography process.
At this time, the second photolithography process may comprise the substeps of coating a photoresist layer on the metal layer, forming a photoresist layer pattern having at least three portions of which thickness are different from each other by exposure and development, and etching the metal layer, the ohmic contact layer, the semiconductor layer and the first insulating layer along with the photoresist layer to remove the first portion that is the thinnest portion of the photoresist layer pattern, and the metal layer, the ohmic contact layer, the semiconductor layer and the first insulating layer thereunder, along with the third portion that is thicker than the first portion, and the metal layer, the ohmic contact layer and the semiconductor layer thereunder, but not to remove the layers under the second portion which is the thickest portion. The exposure of the photoresist layer may be performed by using a photomask including at least three parts of which transmittance are different from each other. The photomask may have slits smaller than the resolution of the stepper or is formed by at least two materials of which transmittance are different from each other. The photomask may be classified into a first mask to form the gate pad and a second mask to form the other area and the transmittance of the first mask is different from that of the second mask. The first portion of the photoresist layer pattern may be located on the gate pad.
The etching step of the metal layer, the ohmic contact layer and the first insulating layer along with the photoresist layer pattern may comprise the substeps of etching the metal layer, the ohmic contact layer, the semiconductor layer and the first insulating layer under the first portion of the photoresist layer pattern by using the second and the third portion as an etch stopper, removing the second portion of the photoresist layer to expose the metal layer thereunder by ashing process, and etching the exposed portion of the metal layer, and the ohmic contact layer and the semiconductor layer thereunder by using the third portion of the photoresist layer as an etch stopper.
The semiconductor layer may be made of amorphous silicon. The second insulating layer may be made of a photo-definable material.
According to the present invention, a thin film transistor array panel may be manufactured by a method comprising the steps of forming a gate wire including a plurality of gate lines and a plurality of gate pads connected to the gate lines on a substrate having a display area and a peripheral area, the gate lines located substantially in the display area and the gate pads located substantially in the peripheral area. The next step is sequentially depositing a gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor layer on the gate wire, coating a photoresist layer on the metal layer, forming a photoresist layer pattern of which thickness is varying depending on the location by exposure and development, patterning the metal layer, the ohmic contact layer, the semiconductor layer and the gate insulating layer at a time to form a metal layer pattern, a first ohmic contact layer pattern and a semiconductor layer pattern and expose the gate pad by a photolithography process. The following step is depositing a conductor layer, forming a conductor layer pattern including a pixel electrode covering a part of the metal layer and a separated conductor layer pattern covering the other part of the metal layer and located at the opposite side of the pixel electrode with respect to the gate electrode by a photolithography process. The next step is removing the portion of the metal layer between the pixel electrode and the separated conductor layer pattern and the ohmic contact layer thereunder to form a data wire including a plurality of data lines, data pads, source electrodes and drain electrodes, and a second ohmic contact layer pattern thereunder. And the final step is forming a passivation layer.
At this time, the photoresist layer pattern may be formed only in the display area and on the metal layer pattern, the thickness of the photoresist layer pattern is thicker on the metal layer pattern than elsewhere of the display area. The step of patterning the metal layer, the ohmic contact layer, the semiconductor layer and the gate insulating layer at a time may comprise the substeps of removing the exposed portion of the metal layer in the peripheral area to expose the ohmic contact layer, removing the thin photoresist layer in the display area to expose the metal layer thereunder by using an etch method that is able to etch the photoresist layer, the ohmic contact layer and the semiconductor layer at a time. Then, the exposed portion of the metal layer in the display area is removed to expose the ohmic contact layer. The semiconductor layer and the gate insulating layer are etched out to expose the gate pad in the peripheral area and to remove the exposed portion of the ohmic contact layer and the semiconductor layer thereunder by using an etch method that is able to etch the ohmic contact layer, the semiconductor layer and the gate insulating layer at a time.
The passivation layer may have openings exposing the pixel electrode. The conductor layer pattern may include a plurality of redundant data lines covering the data line, redundant data pad covering the data pad and redundant gate pad covering the gate pad. The passivation layer may have openings exposing the redundant gate pad and the redundant data pad. The manufacturing method may further include a step of forming a common wire on the substrate including a plurality of common electrodes that generate electric fields with the pixel electrode.
According to the present invention, a thin film transistor array panel may be manufactured by a method comprising the steps of forming a gate wire including a plurality of gate lines, gate electrodes connected to the gate line and a common wire including a plurality of common electrodes on an insulating substrate, forming a gate insulating layer pattern that covers the gate wire and the common wire, forming a semiconductor pattern on the gate insulating layer, forming an ohmic contact layer pattern on the semiconductor pattern, forming a data wire including a plurality of data lines, source electrodes connected to the data line, drain electrodes separated from the source electrode on the ohmic contact layer pattern, forming a passivation layer pattern covering the data wire except for a part of the drain electrode, and forming a plurality of pixel electrode connected to the drain electrodes and generating electric fields with the common electrode. At this time, the source electrode and the drain electrode is separated by a photolithography process that uses a photoresist layer pattern. The photoresist layer pattern includes a first portion located between the source electrode and the drain electrode, a second portion thicker than the first portion, and a third portion thinner than the first portion.
Furthermore, the data wire, the ohmic contact layer and the semiconductor layer may be formed using a mask. The gate insulating layer, the semiconductor pattern, the ohmic contact layer pattern and the data wire may be formed in the substeps of depositing the gate insulating layer, the semiconductor layer, the ohmic contact layer and the metal layer. A photoresist layer is coated on the metal layer and exposed through the photomask. Then, the photoresist layer is developed to form the photoresist layer pattern. The second portion of the pattern is located on the data wire. The portion of the metal layer, the ohmic contact layer and the semiconductor layer under the third portion are etched out. The second portion is also etched to a certain thickness along with the portion of the metal layer and the ohmic contact layer thereunder. The remaining photoresist layer pattern of the second portion is used for forming the data wire, the ohmic contact layer pattern and the semiconductor pattern. Finally, the photoresist layer pattern is removed. The data wire, the ohmic contact layer pattern and the semiconductor pattern may be formed in the substeps of etching the portion of the metal layer under the third portion to expose the ohmic contact layer by wet etch or dry etch, dry etching the ohmic contact layer under the third portion and the semiconductor layer thereunder along with the first portion to expose the gate insulating layer under the third portion and the metal layer under the first portion along with completing the semiconductor pattern. The portion of the metal layer under the first portion and the ohmic contact layer thereunder are etched out to complete the data wire and the ohmic contact layer pattern.